cadence composer notes

[undo limits]
>> vi ~/.cdsinit

hiSetUndoLimit(10)     

or 

>> vi ~/.cdsenv

ui undoLevel int 10


[parameterized symbol]
fill pPar("parameter") into property boxes
http://www.egr.msu.edu/classes/ece410/mason/files/tutorialD.pdf

[CDL out pin order control]
ref. https://softwareoptimization.wordpress.com/2014/09/05/problem-solved-pin-order-virtuoso-cadence/

Step A:

1. Open the CELL symbol using the Symbol Editor. Open the Pin Order setup by clicking on: EDIT -> Properties -> Pin Order. In the Edit Pin Order window, set the desired pin order. Click on Apply and OK. Save it.  Close the symbol editor.
2. Open the CELL schematic using the Schematic Editor. Open the Pin Order setup by clicking on: EDIT -> Properties -> Pin Order. Select COPY From: Symbol, to get the pin order you set on step [A1]. If you didn’t get the desired pin order, change it manually and save it. Close the schematic editor.
3. Open again (to make sure it was saved) both symbol and schematic and verify if the PIN ORDER is correct. If everything is “ok”, close both editors, if not, fix it by following step [A1] and [A2].

Step B:

1. Check the root where you execute virtuoso (same directory where the cds.lib and .cdsinit are placed) for the file .simrc
   1. If the file (.simrc) doesn’t exist, create the file .simrc in the directory identified before.
2. Edit the file (.simrc) and include the line: auCdlCDFPinCntrl=t
   1. If this line was already included, but with different value, change it. This will make the CDL use your PIN ORDER, instead of the default chosen by Cadence.

Step C:

1. Go to the CIW window, and open the CDF Editor, by clicking on Tools -> CDF -> Edit.
2. In the “Edit CDF” window, select the Scope: Cell, and  CDF Layer: Base.
3. Now select the desired LIBRARY and CELL NAME that you want to change the PIN ORDER. You will have to change the PIN ORDER of each cell individually.
4. After selecting the CELL, select the tab “Simulation Information” and them select “Choose Listing:By Simulator“. Select the simulator “auCdl” .
5. Now edit the fields as follow. Change the pin names “my_pin_1,2,3” for the desired name/order you have chosen. You probably don’t need to change the namePrefix. Consult the CDF documentation if need any additional customization.
   1. netlistProcedure: ansCdlSubcktCall
   2. componentName: subcircuit
   3. termOrder: “my_pin_1” “my_pin_2” “my_pin_3”
   4. namePrefix: X
6. Click on APPLY to confirm the change.
7. Repeat step [C4 to C6] for each desired cell.

! IMPORTANT (STEP C4): The name of the PINS in the “termOrder“, should be enclosed by ” “.  If my cell is a NAND gate with pins A1 A2 ZN, the termOrder will be: “A1” “A2” “ZN”

End:

1. Go to the CIW window, and open the CDL Exporter, by clicking on File -> Export -> CDL . Choose the desired schematic to export and confirm.
2. Verify if the CELL pin order is correct. If not, review STEP A,B,C.
   1. Make sure the Step C was done properly. Close the environment, and open it again. Check if your changes were salved.
    
   

[schematic to layout] IC6
launch -> virtuoso XL -> connectivity -> update -> components and nets...
[ref]
http://www2.ece.rochester.edu/~maricic/autorouter_Cadence_XL.htm
http://web.nchu.edu.tw/~ycchiang/VLSI_Lab/Layout%20fundamental.pdf